A Digital Controlled Multi-Phase Delay Locked Loop with Calibration Technique
碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 97 === This thesis presents a digital-controlled delay line with digital to voltage converter (DVC) to achieve fast locking. In addition, the digital to voltage converter is applied in a digitally controlled Delay Locked Loop (DLL). The advantages of combining digi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21223633502549330752 |