Routing for Network-on-Chip Architectures with Faulty Components
碩士 === 國立東華大學 === 資訊工程學系 === 97 === As CMOS process technology advances, a single chip will accommodate more than one billion transistors. Traditionally, using bus as a communication interface is common, but will become a major performance bottleneck for system-on-chip designs. Therefore, network-on...
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| Format: | Others |
| Language: | zh-TW |
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2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78713135014029891596 |