A Real-time VLSI Architecture with Embedded SRAM Array for Full Search Block Matching Algorithm
碩士 === 國立彰化師範大學 === 電子工程學系 === 97 === We propose a build-in SRAM array VLSI architecture for Full Search Block Matching Algorithm (FSBMA). In the conventional 2-dimensional (2-D) systolic processing element (PE) array used for motion estimation, sequence data delivered from the external SRAM to the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01704437025466985212 |