Built-in Jitter Measurement Circuits Designs and Applications in Serial-Link Transceivers

• Main Authors: Shu-Yu Jiang, 江書育
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/68178699500639964898

博士 === 國立中央大學 === 電機工程研究所 === 97 === The need for high timing resolution markedly increases test cost and limits feasible designs. To overcome these limitations, the built-in jitter measurement (BIJM) circuit is generally used to measure on-chip signal jitter distribution. Generally, the timing measurement techniques can be separated as two parts, open-loop and close-loop structures. For the open-loop structure, a 2.5 GHz BIJM system is adopted to measure the clock jitter of the serial-link transceiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78 % relative to pure Vernier delay line (VDL) structure with a wide measurement range. The counter circuit occupies an area of 19 x 61 μm2 in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The supply voltage variation rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. Core circuit occupies an area of only 0.5 x 0.15 mm2 with the 90 nm CMOS process. The Gaussian and uniform distributions jitters are verified at a 5 ps timing resolution and a 2.5 GHz input clock frequency. Further, chips implementation is also verified with the 90 nm and 0.35 μm CMOS process. For the closed-loop structure, limitations of BIJM circuit designs include area cost, process variation and supply voltage noise. Conventional Vernier oscillator structure can solve the area cost problem. However, process and voltage variations always introduce noise into BIJM circuit. The proposed split path Vernier winding loop can solve the area cost, process variation and supply voltage noise at the same time. The 10-bit counter/shift register are applied to solve the pin count problem. The proposed split path Vernier cell is inserted into the conventional NAND gate chain for the accuracy improvement. By adding the controllable capacitors on the propagation paths, process and supply voltage variations only slightly affect jitter measurement result. Further, a calibration process is proposed to control the process and supply voltage compensation circuit and eliminate the un-avoidable measurement offset. All of these techniques were verified in the proposed compact and robust BIJM circuit by using the 0.18 μm 1P6M CMOS process. The 500–1300 MHz measurement range requires a chip area of only 0.006 mm2. Measurement accuracy exceeds 95 % for 5 ps timing resolution. Further, power consumption is just 1.7 mW for a 1 GHz input pulse signal.