Design of Low Phase Noise Phase-locked-loop (PLL)
碩士 === 國立中央大學 === 電機工程研究所 === 97 === The chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-L...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/89170514894602135448 |