Design and Implementation of 6-Gb/s Half-Rate Clock and Data Recovery Circuit

Design and Implementation of 6-Gb/s Half-Rate Clock and Data Recovery Circuit

碩士 === 國立中央大學 === 電機工程研究所 === 97 === As the demands for the data rate increase, the input–output (I/O) bandwidth will progress with each passing day. Therefore, the high speed serial I/O systems have replaced traditional parallel I/O systems gradually. For example, 10G Ethernet and OC-192 are applie...

Full description

Bibliographic Details
Main Authors:	Tsung-hui Lin, 林璁輝
Other Authors:	Kuo-hsing Cheng
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/85980333638676163832

Similar Items

A 3.2-Gb/s Low-Power Half-Rate Clock and Data Recovery Circuit
by: Rong-SingChu, et al.
Published: (2011)

A 2.5Gb/s Half-Rate Clock and Data Recovery Circuit for SONET OC-48 Application
by: Yen-Hong Lin, et al.
Published: (2007)

An 8 Gb/s Half-rate Digital-based Clock and Data Recovery Circuit With Compact Control Loop
by: Yu-PoCheng, et al.
Published: (2015)

Design and Implementation of a 3.125-Gb/s Clock Data Recovery Circuit
by: Sun-Ping Chen, et al.
Published: (2003)

1.5Gb/s Clock and Data Recovery Circuit
by: Chen, Jui-Ming, et al.
Published: (2011)

A 25Gb/s clock and data recovery circuit design
by: Chou, You-An., et al.
Published: (2019)

Design and Analysis of 2.5-Gb/s and 5-Gb/s Clock and Data Recovery Circuits
by: Wu,Chi-Hsien, et al.
Published: (2018)

An Inductorless Half-Rate Clock and Data Recovery Circuit
by: Tang-Lam Wong, et al.
Published: (2011)

Design and Implementation of 6 Gbps Half-Rate Clock and Data Recovery Circuit for SATA-III Application
by: Bing-hung Chen, et al.

Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits
by: Rennie, David J.
Published: (2007)

Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits
by: Rennie, David J.
Published: (2007)

A 1.5-6 Gb/s Clock and Data Recovery Circuit Reducing Cycle Slipping
by: Wei-Liang Lin, et al.
Published: (2019)

Design and Implementation of CMOS 10Gb/s Clock-and-Data Recovery Circuit for OC-192 System
by: Chia-Huang Fu, et al.
Published: (2004)

Design and Application of a 1.25 Gb/s Clock and Data Recovery Circuit
by: Yu Ming-Shih, et al.
Published: (2002)

Design of 1.25 to 2.5 Gb/s Clock and Data Recovery Circuits
by: Guan-Yung Chen, et al.
Published: (101)

Design and Analysis of Tens of Gb/s Multi-Channel Clock and Data Recovery Circuits
by: Chien-Kai Kao, et al.
Published: (2014)

10Gb/s Clock and Data recovery circuit with improved MCML latch
by: 邱俊宏
Published: (2006)

A 3-Gb/s 1/3-Rate Fully Differential Clock and Data Recovery Circuit with an Adaptive Equalizer
by: Yen-Chen Lin, et al.
Published: (2018)

A 20Gb/s Integrating Type Optical Receiver with Baud-Rate Clock and Data Recovery Circuit
by: Lee, Yuan-Sheng, et al.
Published: (2017)

Design and Realization of a 1.25Gb/s Quarter Rate Clock and Data Recovery
by: Jian-Hua Lin, et al.
Published: (2006)

Design and Implementation of 3.125Gb/s Clock and Data Recovery Circuit Using Delay-Chain Frequency Detector
by: Yen-Ting Liu, et al.
Published: (2007)

Clock and Data Recovery Circuit with Improved Half-Rate Linear Phase Detector
by: Chun-Yung Cho, et al.
Published: (2007)

Design and Implementation of 1.25-5.84 Gb/s Reference-Less 1/4-Rate Clock and Data Recovery Circuit for M-PHY Application
by: Zhi-Xin Lin, et al.
Published: (2017)

Design and Implementation of Clock and Data Recovery Circuit
by: Zong-Jin Yang, et al.
Published: (2006)

A 2.5Gb/s Clock and Data Recovery Circuit Using Oversampling and Frequency-Calibrated Techniques
by: Wei-Shuo Lin, et al.
Published: (2010)

A 1/2.5-Rate Clock and Data Recovery Circuit for 100Gb/s Ethernet in 40 nm Technology
by: Chia-Kai Cheng, et al.
Published: (2016)

A 1.25-Gb/s Clock and Data Recovery Circuit for High-Speed Serial Links
by: Cheng-Hsing Lee, et al.
Published: (2004)

A 10-Gb/s CMOS Clock and Data Recovery Circuit with Data-Deskew Buffers in the Closed Loop
by: Chung Chieh Yang, et al.
Published: (2007)

Continuous Rate Clock and Data Recovery Circuit
by: Kuan-Hua Chao, et al.
Published: (2004)

An 8Gb/s Clock and Data Recovery Using Eye-Opening Monitor Technique
by: Hui-Wen Hung, et al.
Published: (2010)

A 1.25Gb/s Burst-Mode Clock and Data Recovery Circuit Using the Jitter Reduction Technique
by: Kae-Dyi You, et al.
Published: (2009)

Tens-Gb/s Decision-Feedback Equalizers and Clock and Data Recovery Circuits for High-Speed Wire-Line Communications
by: Chang-Lin Hsieh, et al.
Published: (2011)

A Quarter Rate Clock and Data Recovery Circuit
by: You-Chun Chang, et al.
Published: (2010)

Design and Implementation of All-Digital Clock and Data Recovery Circuit
by: Chi Min Chiu, et al.
Published: (2010)

Design and Implementation of Burst-Mode Clock and Data Recovery Circuit
by: Liu, Kun-Han, et al.
Published: (2016)

Design and Implementation of CMOS Clock Generation and Clock/Data Recovery Circuits for Wired-line Transceivers
by: Rong-Jyi Yang, et al.
Published: (2006)

A 5Gb/s Clock and Data Recovery with Mixer-Based Phase Detector
by: Soh, Sze-Khiong, et al.
Published: (2019)

A 2.5 Gb/s SONET clock and data recovery macro cell
by: Dickson, Andrew Holden
Published: (2007)

A 10 Gb/s Clock and Data Recovery with PAM-4 Data Phase Detection and Recovered Data Selection
by: Hsiu-Hua Lin, et al.
Published: (2019)

10Gb/s Bang-Bang Clock and Data Recovery (CDR) for optical transmission systems
by: N. Dodel, et al.
Published: (2005-01-01)