Design and Implementation of 6-Gb/s Half-Rate Clock and Data Recovery Circuit
碩士 === 國立中央大學 === 電機工程研究所 === 97 === As the demands for the data rate increase, the input–output (I/O) bandwidth will progress with each passing day. Therefore, the high speed serial I/O systems have replaced traditional parallel I/O systems gradually. For example, 10G Ethernet and OC-192 are applie...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/85980333638676163832 |