| Summary: | 碩士 === 國立交通大學 === 奈米科技研究所 === 97 === Recently, multiple gate structures has been widely studied to increase channel controlability and to overcome limitations in device scaling down. In past study, Gate-All-Around structure in TFT has been proposed to improve channel controllability, to suppress short channel effect (SCE), and to increase device performance due to corner effect. In this thesis, gate-all-around (GAA) poly-Si nanowire (NW) TFTs with SONOS-type memory was demonstrated. The GAA structure is being used to not only increase the device performance but also create corner effect around the nanowire channel. It raises the P/E speed of SONOS-type memory, restrains the gate injection efficiency, and improves the fact of “hard-to-erase” in planer devices as flash memory.
After the device fabricated, a comparison of device performance with GAA structure to TriGate structure were presented. It shows that the GAA device has a high driving current, a steep Subthreshold Swing, an absence of DIBL, and a high on/off current ratio, but gate induce drain leakage was serious than the planer device. The memory program and erase efficiency in the GAA device is better than TriGate device due to the increase of corners number. Furthermore, the device endurance and data retention measurement have also been demonstrated.
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