An Architecture for Exploiting Multi-Core Processors to Parallelize Intrusion Detection Systems
碩士 === 國立交通大學 === 電機與控制工程系所 === 97 === In this thesis, we propose a balanced multi-thread NIDS, bmtNIDS, to get a better efficiency when running in a multi-core system. bmtNIDS supports multiple threads for simultaneous packet captures, such a design benefits from reducing data migrations between th...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/67337768943093626926 |