| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 97 === In the integrated circuits design, performance estimation and circuit optimization are two of the most important issues. The method of “Logical Effort Delay Model” allows designers to quickly estimate delay time and optimize logic paths, but the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results in 90nm process, delay time increases 21% while temperature increasing from 0°C to 125°C. In the mean time, delay time increases 2X while supply voltage decreasing from 1V to 0.5V. Thus a simple linear extension of logical effort g, 1/g = (mtt+bt)VDD+C, supporting for temperature t and supply voltage V¬DD variations is presented. The linear characteristic is convenient for designers to calculate and the integration of proposed model and CAD tools is easier. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. Furthermore, each functional block on a chip can be optimized under different PVT conditions through this simple model. After validation, the accuracy of this new extended logical effort model can achieve about 90%.
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