Logical Effort Model Extension with Temperature and Voltage Variations
碩士 === 國立交通大學 === 電信工程系所 === 97 === In the integrated circuits design, performance estimation and circuit optimization are two of the most important issues. The method of “Logical Effort Delay Model” allows designers to quickly estimate delay time and optimize logic paths, but the previous variances...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72050583009180402403 |