| Summary: | 碩士 === 國立交通大學 === 電子物理系所 === 97 === In this thesis, we demonstrated a nano thin film transistors with channel length of 80 nm and high performance fabricated at very low temperature at 300℃. We applied a novel low temperature microwave annealing technique to activate the source/drain junction of nano thin film transistors successfully. Microwave annealing process is a different annealing process from conventional rapid thermal process (RTP) intrinsically. We discover the difference between microwave annealing and the conventional thermal annealing process in the electronic and physical properties of device performance. The low-temperature process of microwave annealing suppresses the excessive diffusion and expansion of dopants during the source/drain activation process. As a result, novel low-temperature microwave annealing process provides a applicable solution for the issue of gate induced drain leakage (GIDL) and short channel effect (SCE). Determining the sheet resistance of gate and source/drain junction by using four-terminal sheet resistance test structure verifies the activation process is accomplished by means of microwave annealing process. On the other hand, due to the property of low-temperature process, microwave annealing would not result in any defect or misfit dislocation at the interface of heterogeneous structure which can be applied to 3D-ICs, transistors with SiGe channel, and other semiconductor compounds.
|
|---|
