System-Level ESD Protection Design in CMOS ICs With Transient Detection Circuits

• Main Authors: Yen, Cheng-Cheng, 顏承正
• Other Authors: Ker, Ming-Dou
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/07857458140945747413

博士 === 國立交通大學 === 電子工程系所 === 97 === System-level electrostatic discharge (ESD) events have become a primary reliability issue in CMOS integrated circuit (IC) products. With more and more complicated design of integrated circuits, such as mixed-signal, mixed-voltage, system-on-chip (SOC), etc, CMOS devices will suffer more electrical transient noises coming from environment and the interior of CMOS ICs. With advanced semiconductor technology of scaled clearance between PMOS and NMOS devices, it has been proven that such electrical transient noises can cause transient-induced latchup (TLU) failure on the inevitable parasitic silicon controlled rectifier (SCR) in CMOS ICs under system-level ESD and electrical fast transient (EFT) tests. The reliability issue of system-level ESD events results from not only the progress of more integrated functions into a single chip but also from the strict requirements of reliability test standards, such as the system-level ESD test standard of IEC 61000-4-2. The microelectronic products must sustain the ESD level of ±8kV (±15kV) under contact-discharge (air-discharge) test mode to achieve the immunity requirement of “level 4” in the IEC 61000-4-2 test standard. The additional noise filter networks, such as the magnetic core, capacitor filter, ferrite bead (FB), transient voltage suppressor (TVS), RC filters, are often used to improve the system-level ESD immunity of microelectronic products. The system-level ESD immunity of CMOS ICs under system-level ESD test can be significantly enhanced by choosing proper noise filter networks. However, the additional discrete noise-bypassing components substantially increase the total cost of microelectronic products. Therefore, the chip-level solutions to meet high system-level ESD specification for microelectronic products without additional discrete noise-decoupling components on the microelectronic products are highly desired by IC industry. This dissertation focuses on the chip-level solutions for the system-level ESD protection design. Several major topics including: (1) investigation on the latchup-like failure of power-rail ESD clamp circuits under system-level ESD tests, (2) clarification of TLU physical mechanism under EFT tests, (3) evaluations of board-level noise filters to suppress TLU, (3) proposed on-chip transient detection circuits, and (5) proposed transient-to-digital converters. In chapter 2, four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-um CMOS process and tested to compare their system-level ESD and EFT susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD and EFT tests, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a “latch-on” state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD and EFT tests. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD and EFT tests. In chapter 3, the occurrence of TLU in CMOS ICs under the EFT tests is studied. The test chip with the parasitic SCR structure fabricated by a 0.18-um CMOS process was used in the EFT tests. For physical mechanism characterization, the specific “sweep-back” current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved. In chapter 4, a novel RC-based on-chip transient detection circuit for system-level ESD and EFT protection are proposed in this work. The circuit performance to detect positive and negative electrical transients under system-level ESD and EFT testing conditions has been investigated by the HSPICE simulation and verified in silicon chip. The experimental results have confirmed that the proposed on-chip transient detection circuit can successfully memorize the occurrence of the system-level ESD and EFT events. The detection output of proposed on-chip transient detection circuits can be used as the firmware index to execute system recovery procedure to provide a hardware/firmware co-design to improve the immunity of CMOS IC products against electrical transient disturbance. In chapter 5, a new on-chip transient detection circuit for electrical fast disturbance protection design is proposed in this work. The circuit performance to detect different positive and negative ESD-induced or EFT-induced transient disturbance has been investigated by the HSPICE simulation and verified in silicon chip. The EFT generator combined with attenuation network and capacitive coupling clamp has been used as the evaluation method to verify the detection function of the proposed on-chip transient detection circuit under EFT tests. The test chip in a 0.18-um CMOS process with 1.8-V devices has confirmed that the proposed on-chip transient detection circuit can successfully detect and memorize the occurrence of the transient disturbance under system-level ESD or EFT tests. In chapter 6, a novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18-um CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. These output digital codes can be used as the firmware index to execute different auto-recovery procedures in microelectronic systems. Thus, the proposed on-chip transient-to-digital converter can be further combined with firmware design to provide an effective solution to solve the system-level ESD and EFT protection issue in microelectronic systems equipped with CMOS ICs. Chapter 7 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter.