Investigation on the Performance Improvement and Geometric Effects of Nanoscale CMOS Devices with SMT (Stress Memorization Technique)
碩士 === 國立成功大學 === 光電科學與工程研究所 === 97 === Implementation of strained-Si MOSFETs with optimum low cost stress-memorization technique for 40nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with <100> channel orientation provides additional 8% current drivability i...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52728166206963343927 |