A Novel Memory Arrangement Scheme for Low-Complexity LDPC Decoder Design
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === Memory management plays an important role in system/component designs and it is not surprised that memory occupies a large portion of the chip area in pervasive electronic products now. In this work, we propose an efficient memory management scheme for low-den...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84699107457587758649 |