| Summary: | 博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 97 === This dissertation includes two parts for nanometer scale CMOSFET device and ULSI technology studying: (1) nano-scale MOSFET enhancement by strained silicon techniques and (2) the process optimization for Cu interconnect reliability.
Firstly, varied device enhancement technology including strained silicon techniques, like global strain and local strain, and substrate orientation, for example of substrate surface orientation and channel orientation, are detailed studied for its pros and cons on device performance.
A novel hybrid process-induced strain techniques by using tensile contact-etch-stop layer (CESL) along <100>-channel direction on (100) surface orientation wafer has demonstrated 11% and 35% driving current enhancement for both bulk NMOS and PMOS simultaneously at gate length/width 80nm/0.6mm. Superior current driving as high as 917 mA/mm and 436 mA/mm for CMOS respectively is achieved at 1.7 nm gate oxide, 80 nm gate length and operation voltage 1.2V. Both narrow width effect (NWE) and reverse narrow width effect (RNWE) are significantly suppressed for PMOSFET and NMOSFET. Excellent gate delay and IDDQ are also improved up to 16% and 33% respectively from inverter ring oscillator (RO) and one microprocessor.
Secondly, the reliability of Cu interconnection in ULSI technology is studied in detail including IMD, Cu barrier layer, Cu dielectric capping layer and electromigration mechanism. In the following, the effects of surface clean process on stressvoiding (SV) and electromigration (EM) of Cu dual damascene metallization are studied. Prior to the deposition of copper diffusion barrier metal, conventional argon bombardment is used to clean Cu surface. Higher pre-clean bias-power and shorter pre-clean time demonstrate remarkable low via resistance and excellent Cu reliability performance. Also, the via diameter effect to Cu stressmigration (SM) is explored. A superior Cu pre-cleaning process condition is developed to improve Cu stress-induced voiding (SIV) and electromigration (EM). The pre-clean bias power of argon plasma should be kept as high as possible but not too high to avoid damaging underlying metal, while the re-sputtering clean time should keep as short as possible but sufficiently long in order to clean via bottoms. To improve ULSI yield and reliability of Cu damascene metallization, the cleaning process of Cu surface becomes more and more critical as CMOS technology continues shrinking
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