Performance Enhancement of Nanoscale CMOSFET and Process Optimization of Copper Interconnection for ULSI Technology
博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 97 === This dissertation includes two parts for nanometer scale CMOSFET device and ULSI technology studying: (1) nano-scale MOSFET enhancement by strained silicon techniques and (2) the process optimization for Cu interconnect reliability. Firstly, varied device en...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21140106256736496859 |