| Summary: | 博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 97 === In this thesis, the trapping characteristics of positive bias temperature instability (PBTI) on a high-k/metal gate n-type metal oxide semiconductor field effect transistor (nMOSFET) have been firstly investigated with a complementary multi-pulse technique (CMPT) in detail. With the CMPT technique, we find that the threshold voltage shifts after PBTI are higher than that with the conventional direct current method, and the thickness of the SiO2 interfacial layer has a significant effect on the measured results. The observation of these new results is attributed to the CMPT technique has the unique feature of effectively reducing the detrapping effect induced by the large bulk traps existed in high-k dielectrics. Besides, based on the results, the mechanism of PBTI in metal gate/high-k nMOSFETs is modeled. Furthermore, with the terrace high-k method and the frequency-dependent charge pumping technique, the profile of bulk traps in the Hf-based dielectric is sketched to further understand the mechanism of trapping in high-k dielectrics.
Secondly, the bias temperature instability of dual metal gate CMOSFETs with Hf-based dielectrics including HfO2 and HfSiON has been extremely investigated. The influences of high-k gate stacks engineering including zirconium and nitrogen incorporation on performance and BTI of high-k/metal gate MOSFET are studied. We find that the density of bulk traps is reduced with increasing Zr content with a comparable Dit value. Consequently, mobility increases with increasing Zr content in the HfZrOX dielectric and ~25% mobility enhancement compared with that of HfO2 can be observed. The improvement in PBTI is also demonstrated with DC and pulse techniques. The smaller Vth shift in PBTI is attributed to the reduction of fast trapping and the generation of slow traps. On the other hand, experimental results revealed the high-k dielectric nitrogen annealing is a better solution for the trade-off between mobility and inversion oxide thickness (TOX, INV) than IL nitrogen annealing. In addition, the positive bias temperature instability (PBTI) characteristic is improved through reducing the quantity of bulk traps. However, the high-k dielectric nitrogen annealing also lowers the barrier of dielectric and thus results in an abnormally higher leakage current. Furthermore, the strain effect from a tensile SiN capping layer, as well as the channel length dependence, on both NBTI and PBTI of the high-k gate stack devices are studied. For channel length larger than 0.1 µm, both PBTI and NBTI are not affected by the tensile strain obviously. As the channel scaling down to less than 0.1 µm, the degradation after PBTI stress is still not influenced by the strain, however, the NBTI degradation is enhanced significantly. In addition, the dependence of BTI on channel length is extensively investigated under constant voltage and field stress.
Thirdly, a comprehensive study on bulk trap enhanced gate induced drain leakage currents (BTE-GIDL) in high-k MOSFETs is reported. The dependence of GIDL for various parameters including the effect of Zr concentration in HfZrOX, high-k film thickness, and electrical stress is investigated. The incorporation of Zr into HfO2 reduces GIDL. GIDL is also found to reduce with thinner high-k film. In addition, a significant correlation between GIDL and bulk trap density in high-k film is established. Possible mechanisms are provided to explain the role of bulk trapping in BTE-GIDL. Furthermore, the effects of shallow trench isolation (STI) induce mechanical strain on GIDL current in Hf-based and SiON nMOSFETs are investigated in detail. The STI-induced mechanical strain enhances the GIDL current including the trap-assisted tunneling (TAT) component at low voltage and the band-to-band tunneling (BBT) component at high voltage. The compressive strain induced band narrowing and the increase of intrinsic carrier concentration are attributed to the root cause of GIDL increment, respectively. However, different strain sensitivities of GIDL are observed on HfO2 and SiON nMOSFETs. The higher density of interface states induced by mechanical strain is responsible for the higher strain sensitivity observed on HfO2 devices. The symmetric layout shows higher ability to suppress the STI-enhanced GIDL current with same active area length.
Finally, the dynamic NBTI on low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) is investigated in detail. Experimental results reveal the threshold voltage shift of LTPS TFTs after the NBTI stress decreases with increasing frequency, which is different to the frequency-independent of conventional CMOSFET. The difference of transit time between grain boundary and Si/SiO2 interface dominates the LTPS TFTs dynamic NBTI behaviors and results in the dependence of frequency.
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