Design of Low Power Dual-Path PS-LDPC Decoder
碩士 === 國立中興大學 === 通訊工程研究所 === 97 === In this thesis, a design of low power high throughput dual-path PS-LDPC decoder is presented. The (512, 1024) check matrix is a regular matrix whose column weight and row weight are 3 and 6, respectively. There are four units including a variable node unit (VNU),...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24053224863620309077 |