Trend Shift of Degradation Mechanisms of Various Annealing CLC Poly-Si n-TFTs under DAHC Stress and Temperature Enhancement

• Main Author: 鄧怡群
• Other Authors: 王木俊
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/74811396136410802583

碩士 === 明新科技大學 === 電子工程研究所 === 97 === Polycrystalline silicon TFTs （Poly-Si TFT） propose the higher electron mobility, therefore, the hot-carrier effect under the high-voltage operation is still a device reliability issue. In this study, the drain-avalanche hot-carrier （DAHC） effect plus temperature variation on continuous-wave green laser- crystallized （CLC） poly-Si N-TFTs was investigated. The degradation phenomenon of device characteristcs after stress was observed. The stressed devices with green-laser anneal were chosen. This process effectively promoted the channel mobility in N-TFTs. The source/drain activation contains laser activation or furnace activation usually on glass substrate. In device characteristics and reliability issues, the main focus was related to the gate oxide integrity and the degradation mechanisms of DAHC effect with the temperature enhancement. The investigation was to probe the moving behaviors of electrons and holes. In experiment, the electron mobility with laser activation is higher than that with furnace activation. Therefore, the transistor switching performance in the previous is also better. For a system-on-insulator （SOI） device, the bulk electrode is floating. Thus, the substrate current can not be easily observed. Using the shifts of C-V curves and observing the curve variation before-and-after stress, the quantity of interface states and bulk traps can be realized. Indirectly, the degradation level of device is ableto be justified. Furthermore, the gate-to-source capacitance CGS and the gate-to-drain capacitance CGD show some deviation before-and-after stress. Some frequency operation impacting the C-V curves is also summarized and exposes the correlated factors in this study.