Implementation of a JPEG Encoding System on Chip Using the MIPS-like Architecture
碩士 === 大葉大學 === 電機工程學系 === 97 === JPEG encoding is wildly applied in present 3C products such as digital camera and mobile phone. This study develops a 32-bits RISC (Reduced Instruction Set Computer) microprocessor with the MIPS-like architecture embedded a JPEG encoder by using the Verilog HDL (Har...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49066656535834809241 |