| Summary: | 碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 97 === ABSTRACT
In this thesis we design a frequency synthesizer based on phase-locked- loop. The PLLs are important components widely used in the electronic and communication circuits. They are used to solve the clock skew and frequency synthesis problems of ICs in a fast operation speed and highly integrated environment. The application of the frequency synthesizer is extensive, for example: Television select platform device, so long as wireless network card ,etc. concern locking of frequency have existence of it, the purpose of this thesis lies in recommending the theory of the frequency synthesizer to analysis and the actual design process of a frequency synthesizer.
The TSMC 0.35 um BiCMOS Mixed Signal SiGe 2P4M process is used to implement the frequency synthesizer； its consumption power of the frequency synthesizer is 40mW with the 3.3V power supply. A wide range of ring VCO operation frequency, 1.1GHz-2.8GHz, is designed to ensure that the VCO still can generate the desired frequency even when the process conditions vary. Simulation results demonstrate that the synthesizer obtains a steady output signal under dierent corner models. The phase noise is obtained to be -106dBc/Hz.
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