Design and Analysis of Phase-Locked-Loop-Based Frequency Synthesizer
碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 97 === ABSTRACT In this thesis we design a frequency synthesizer based on phase-locked- loop. The PLLs are important components widely used in the electronic and communication circuits. They are used to solve the clock skew and frequency synthesis problems of ICs in a...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85399902295213114533 |