FPGA-based digital calibration algorithms in a two-channel time-interleaved analog-to-digital converter
碩士 === 國立中正大學 === 電機工程所 === 97 === A digital calibration scheme for the two-channel time-interleaved analog-to-digital converter (ADC) is designed and implemented in a FPGA-based environment. The non-ideal effects among the time-interleaved ADCs, such as gain errors and bandwidth mismatches, degrade...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28665034116788207972 |
| Summary: | 碩士 === 國立中正大學 === 電機工程所 === 97 === A digital calibration scheme for the two-channel time-interleaved analog-to-digital converter (ADC) is designed and implemented in a FPGA-based environment. The non-ideal effects among the time-interleaved ADCs, such as gain errors and bandwidth mismatches, degrade the overall signal-to-noise ratio (SNR) of the ADCs. Background calibration is a well-known technique to overcome these errors. Digital equalizer is adopted to compensate the gain errors and bandwidth mismatches among the time-interleaved channels. Adaptive least mean square (LMS) algorithm is utilized in the digital calibration so that the digital equalizer could converge to minimize the errors. The behavior model of the digital calibration algorithm is simulated in Matlab. The digital calibration scheme is realized with Verilog and then synthesized in TSMC 0.13μm 1P8M CMOS technology, including placing and routing. Finally, the FPGA-based digital calibration scheme is tested, and the measured results are sent to Matlab to calculate the SNDR. The measurement shows that the digital calibration algorithm is robust and accurate.
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