FPGA-based digital calibration algorithms in a two-channel time-interleaved analog-to-digital converter
碩士 === 國立中正大學 === 電機工程所 === 97 === A digital calibration scheme for the two-channel time-interleaved analog-to-digital converter (ADC) is designed and implemented in a FPGA-based environment. The non-ideal effects among the time-interleaved ADCs, such as gain errors and bandwidth mismatches, degrade...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28665034116788207972 |