Bus Arbiters of the VC-1 Encoder and Decoder

• Main Authors: Wei-Cheng Cheng, 程偉政
• Other Authors: Oscal T.–C. Chen
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/89780672286158088262

碩士 === 國立中正大學 === 電機工程所 === 97 === In this dissertation, the bus arbiters for the Video Codec 1 (VC-1) are successfully implemented on the Field Programmable Gate Array (FPGA) platform. Particularly, there are three versions of the bus arbiter for the VC-1 decoder and one version of the bus arbiter for the VC-1 encoder. First, the data flows, memory organization and timing arrangement of the bus arbiter are introduced in detail where the addressing mechanism of the bus arbiter depends on the memory types. Second, the implementation manners of the bus arbiters are clearly illustrated. The verilog codes of the bus arbiters are synthesized by the Xilinx synthesis tool, and then simulated by the ModelSim software to verify their functionalities. Third, the proposed bus arbiters integrated with the other modules of the VC-1 codec at different profiles are demonstrated. Additionally, the total equivalent gate counts of the bus arbiters at four versions are explored. From the practical results, the proposed bus arbiters can effectively and correctly conduct the data accessing and manipulation for the VC-1 codec on various multimedia applications.