Bus Arbiters of the VC-1 Encoder and Decoder
碩士 === 國立中正大學 === 電機工程所 === 97 === In this dissertation, the bus arbiters for the Video Codec 1 (VC-1) are successfully implemented on the Field Programmable Gate Array (FPGA) platform. Particularly, there are three versions of the bus arbiter for the VC-1 decoder and one version of the bus arbiter...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/89780672286158088262 |