A Case Study of Memory Device ESD (Electrostatic Discharge)Circuit Failure Analysis

• Main Authors: Yu-Min Chung, 鍾尤敏
• Other Authors: Hsiu-Li Lin
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/80186024986097191240

碩士 === 元智大學 === 化學工程與材料科學學系 === 96 === Device reliability is getting worse since the thickness of gate oxide is getting thinner, and the Integrated Circuits (ICs) are much more easily to be damaged comparing with the devices fabricated before. This thesis is to investigate a SRAM (Static Random Access Memory) product which returning from customer for failure analysis and was suspected to have weakness in circuit designing. By applying Latch-up and Electrical Over stress (EOS) tests, the failure phenomena in customer site can be duplicated successfully, and the EOS event is considered the root cause of device failure. Liquid Crystal (LC) and Emission Microscope (EMMI) were used to localize the current surge location in this investigation. It is found that the ESD protection circuit turns on at 7.2V, which results in a large current and burns the metal line due to its current density was too high. Two methods were used to improve the EOS tolerance. The first method is mask changing to modify the layout and create another path for current discharging. The result was not as what was expected, and the layout modification was not taken into consideration since there is space limitation. The second method is ESD protection circuit implantation dosage modification. The EOS tolerance can be improved to 10V by removing the implantation process, but the ESD immunity was degraded and could not pass 2000V test which is the requirement for commercial grade ICs. Finally by decreasing the implantation dosage to 50% of the origin, the EOS tolerance can be improved to 7.7V and also can pass the commercial grade ESD test specification. The modified factor has been put into production, and the EOS induced failure is supposed to reduce in customer site in the future. In this thesis, the weakness of the circuitry design of a SRAM product is studied. Appropriated separating the ESD protection circuits in a limited area is recommended to the designer and the width of the metal interconnect should also be considered. According to the high power ICs, applying EOS test on new design product is considered to include before mass production.