A Compact Comparator Circuit Design for Min-Sum Algorithm of Low Density Parity Check Decoder

• Main Authors: Chen-Pang Chang, 張鎮邦
• Other Authors: Po-Hui Yang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/a7q4t2

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 96 === This thesis proposed a kind of new simplified comparator circuit applied in the Check-Node unit of the Low-Density Parity-Check Code (LDPC) decoder. This new comparator, consisting of logical judgment circuit, multiplexer and basic logic AND function, replaces the traditional comparators used in the Check-node unit, so that it reduce the hardware area and improves operational frequency at the same time. In the Check-Node unit alone, synthesized in a 0.18μm CMOS cell based technology, the hardware area saves about 55% to 62%, and the operational frequency improved by 2 to 3 times, in different bit-lengths. As to the LDPC decoder, the whole hardware adopting new comparator in Check-node unit saves 11% to 15%. An IEEE 802.16e irregular code standard application, H-matrix setting as (576,288) and code rate setting as 1/2, is the main target of this thesis. Simulation results under the fixed iteration number of times show that the Bit Error Rate can be equally good with traditional Min-Sum. When SNR is 2.5dB, the BER difference is only 0.06dB. An ASIC, equipping with self-test mechanism and automatic generate AWGN circuit, has been implemented by a 0.18μm CMOS cell based technology, and verified the success of new comparator finally.