A Compact Comparator Circuit Design for Min-Sum Algorithm of Low Density Parity Check Decoder
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 96 === This thesis proposed a kind of new simplified comparator circuit applied in the Check-Node unit of the Low-Density Parity-Check Code (LDPC) decoder. This new comparator, consisting of logical judgment circuit, multiplexer and basic logic AND function, replac...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/a7q4t2 |