| Summary: | 碩士 === 雲林科技大學 === 電子與資訊工程研究所 === 96 === In modern SoC designs, a lot of reusable IPs are usually employed to shorten the design cycle. However, due to the varities of IP designs, they may each work in a different clock domain, which complicates the IP integration problem significantly. How to cope with signal propagation/synchronization problems in the context of multi-clock domain is thus essential to the IP integration.
In this thesis, we propose an asynchronous FIFO based interface design schemes to tackle the IP integration problem under clock domain crossing (CDC). The proposed asynchronous interface template can provide functions of protocol translation, data buffering and data width conversion. The interface controller adopts a split protocol design approach and consists of several FSMs. The asynchronous FIFO supports read/write accesses in different clock domains and is used as the data passing mechanism between the two sites. Based on the proposed asynchronous interface template, an asynchronous interface bridge design methodology is developed and an AHB-to-PCI ridge design is employed to verify the scheme.
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