Asynchronous Interface Designs for IP Integration in SoC
碩士 === 雲林科技大學 === 電子與資訊工程研究所 === 96 === In modern SoC designs, a lot of reusable IPs are usually employed to shorten the design cycle. However, due to the varities of IP designs, they may each work in a different clock domain, which complicates the IP integration problem significantly. How to cope w...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44377075767868375082 |