| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 96 === To design a PLL must consider several conditions as the following：1. Low-jitter. 2. Low-power. 3. Wider linearity region. 4. Fast-locked. The thesis focuses on Fast-locked.
Therefore, this thesis presents the analog adaptive PLL architecture with a new adaptive controlled detector to reduce locking time and low jitter in PLL stably. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status.
The proposed architecture is realized in a standard TSMC 0.18 1P6M CMOS technology. The locking time is approximately 800ns and is reduced over 50% than the conventional PLL, power consumption is about 23mW and jitter magnitude is about 24ps on 2GHz.
Keywords：adaptive, fast-locked, low jitter, PLL.
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