AN ADAPTIVE BANDWIDTH AND STABLE CONTROL FOR FAST LOCKED PLL
碩士 === 大同大學 === 電機工程學系(所) === 96 === To design a PLL must consider several conditions as the following：1. Low-jitter. 2. Low-power. 3. Wider linearity region. 4. Fast-locked. The thesis focuses on Fast-locked. Therefore, this thesis presents the analog adaptive PLL architecture with a new adaptive c...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25151217268757139112 |