A New Scan Chain Clock Gating for Capture Power Reduction
碩士 === 淡江大學 === 電機工程學系碩士班 === 96 === Recently, low power implementation is a great challenge in scan-based testing. Many previous researches are focus on shift power reduction, only a few are taking capture power into consideration. In capture mode, excessive IP-drop may occurred due to the high swi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51596025142023446059 |