| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the problem of the power consumption, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper), and CAM (Content-Addressable Memory) is an indispensable part in the router. In this thesis, we propose a NOR-type logic Content-Addressable Memory circuit of two segment matchline scheme to Reduce power consumption, in this thesis, the proposed matching scheme can be saved about 70% on average power consumption.
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