High-Level Power Optimization of Low-PowerLarge-Size Multiplier Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === As integrated-circuit (IC) technology advances to into deep-submicron (DSM) regime, more functionality can be combined into a single chip. To design such a complex device, low power consumption has become a significant requirement. If you want to design a high p...
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| Format: | Others |
| Language: | zh-TW |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74003714665656814451 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === As integrated-circuit (IC) technology advances to into deep-submicron (DSM) regime, more functionality can be combined into a single chip. To design such a complex device, low power consumption has become a significant requirement. If you want to design a high performance circuit, you should keep power consumption.
The paper describe a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique using Synopsys PrimeTime tool for designing high-speed low-power SOC applications dealing with 90nm MTCMOS technology. The cell libraries come in fixed threshold - high Vt for low static power and low Vt for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library. And then we get the optimized 16 bits multiplier to combined a large size 32 bits multiplier. We can get the good result ─ 50% less leakage power consumption using 16 bits or 32bits multiplier.
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