High-Level Power Optimization of Low-PowerLarge-Size Multiplier Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === As integrated-circuit (IC) technology advances to into deep-submicron (DSM) regime, more functionality can be combined into a single chip. To design such a complex device, low power consumption has become a significant requirement. If you want to design a high p...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74003714665656814451 |