Low Transmission Latency Method for 2D-mesh NoC Architecture
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === With the development of deep submicron chip technology, a chip can pack more than a billion transistors nowadays. This capacity will allow the System-on-Chip (SoC) designs with a large amount of IP cores on a single chip. However, the inter-communication between...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/03942378007544307436 |