Evaluating 3D Lithographic and Electromagnetic Simulation Software as the Nanometer Physical Layout Tools

• Main Authors: Fu-Yen Hsiao, 蕭輔諺
• Other Authors: Keh-Jeng Chang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/48262131642229757274

碩士 === 國立清華大學 === 資訊工程學系 === 96 === Decreasing on the device size is the trend of the current semiconductor industry. Advanced process continues following with the Moore’s law and the semiconductor process moves from the sub-micro process into the nanometer process. Hence, the challenges about the circuit design and manufacturing grow up and the complexity inside the chip is also increasing. Among the challenges in the process steps, error happens in the lithographical step is the most critical and vital problem. Nowadays advanced nanometer process steps, exposed silicon image is not able to near our needs easily. Therefore, there are many resolution enhancement technologies developed which can decrease exposed error to meet our expectation. We generate and analyze the electrical effect data and aerial image error data after lithography process step by using software simulation. After circuit layout completion, if we could execute the lithography simulation which uses lithography process settings provided by foundry, we could get the simulated silicon image and electrical data. After that, we could find out the differences and critical parts between the simulated information and the ideal ones. Finally, designers could adopt the information to improve their design. It helps rising the yield and time to market. We proposed a flow that adopts lithography simulation software to help designers. The flow includes a lithography engine and a field solver, Clever from Silvaco. It can help facing the challenges early in lithography step for nanometer circuit process and also avoiding the yield falling down. We take a ring oscillator circuit which contains seven inverters to be our test case. Ring oscillator circuit is a popular test structure in foundry manufacturing process. It is almost impossible to obtain industrial OPC technologies and industrial nanometer process parameters. With the said difficulties, we managed with hard-working to obtain reasonable data for our experiments. We also deeply appreciate National Taiwan University professor Tsai and Southern Taiwan University professor Tang who gave us many help and their OPCed example. Finally we quantify the exclusive or image data and electrical data after the aerial simulation and electrical extraction, respectively. We made the conclusion about the capacitance increasing along with process advancing and a graphic exclusive-or (XOR) operation to speed up the OPC design.