Low Power, Fast Locking, and Wide-Range Delay-locked Loop for Clock Generator.
碩士 === 國立中山大學 === 資訊工程學系研究所 === 96 === This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/ej3xpb |