Design of Pipelined VLSI Circuits for Tolerating Timing Errors

Design of Pipelined VLSI Circuits for Tolerating Timing Errors

碩士 === 國立東華大學 === 電子工程研究所 === 96 === Abstract Owing to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting more and more seve...

Full description

Bibliographic Details
Main Authors:	Yi-Kai Wang, 王逸凱
Other Authors:	Chou-Chi Hsin
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/85736205639217314454

Similar Items

Design of VLSI Circuits for Tolerating Soft Errors
by: Jhih-Ping Shiou, et al.
Published: (2008)

Design of Pipelined Circuits for Tolerating Multiple Timing Errors
by: Ｍin-Sheng Gu, et al.
Published: (2009)

Design of Timing-Error-Tolerant VLSI Circuits for RSA Encryption and Decryption
by: Tsung-Han Wu, et al.
Published: (2014)

VLSI Design of a Timing-Error-Tolerant Microprocessor
by: Guan-Lin Peng, et al.
Published: (2016)

Design of Elastic Pipelines for Tolerating Timing Errors
by: Shao-Hsien Lin, et al.
Published: (2010)

An Error-Tolerant Dynamic Voltage Scaling Method for Low-Power Pipeline Circuit Design
by: Han, Qiang
Published: (2012)

Emota:an event-driven MOS timing simulator for VLSI circuits
by: TAO, YI-XIN, et al.
Published: (1988)

Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits
by: Shim, Kyu-Nam 1978-
Published: (2013)

Design and test for timing uncertainty in VLSI circuits.
Published: (2012)

Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits
by: Gill, Balkaran S.
Published: (2006)

VLSI design for pipelined FFT processors
by: Stuart, David Charles
Published: (2013)

VLSI Design of Timing-Error-Resilient Sorting Hardware
by: Chu-Wen Wu, et al.
Published: (2016)

Pipeline Banyan: design, analysis and VLSI implementation.
Published: (1994)

A high-speed pipeline VLSI architecture for reed-solomon decoder
by: LIN, SHENG-KAI, et al.
Published: (1992)

Probabilistic Error Analysis Models for Nano-Domain VLSI Circuits
by: Lingasubramanian, Karthikeyan
Published: (2010)

Architectures and Algorithms for Mitigation of Soft Errors in Nanoscale VLSI Circuits
by: Bhattacharya, Koustav
Published: (2009)

Probability of latching single event upset errors in VLSI circuits
by: Holland, Kenneth Chris
Published: (2014)

The expandble vlsi circuit implementation of the kohonen neural network
by: GUO, WEN-KAI, et al.
Published: (1992)

Design of Soft Error Tolerant Circuits and Architectures
by: Chien Chang Peng, et al.
Published: (2015)

VLSI Design and Implementation of Pipelined Two's Complement Multiplier
by: Liu, Fun Jen, et al.
Published: (1994)

A Pipelined VLSI Design of the Reed-Solomon Decoder
by: Hwang, Tsong Der, et al.
Published: (1993)

VLSI Circuit Design of Karatsuba’s Multiplier
by: Chu-Hsin Huang, et al.
Published: (2004)

Parallel pipelined VLSI arrays for real-time image processing
by: Ali, Faridah M.
Published: (2014)

Soft Error Analysis of VLSI Designs considering Advanced Effects – from Device to Circuit Level
by: Huang, Hsuan-Ming, et al.
Published: (2015)

Design and timing analysis of wave pipelined circuits
by: Ozgun, Recep
Published: (2006)

Analog VLSI circuit design of spike-timing-dependent synaptic plasticity
by: Monzon, Joshua Jen C
Published: (2010)

The design and implementation of VLSI circuits for hearing aid applications
by: Yi, Jian Yu, et al.
Published: (1995)

The design and analysis of new digital comos logic circuits for VLSI applications
by: WANG, JIN-XIAN, et al.
Published: (1988)

A VLSI Chip for Stage-Pipelined Implementation of Large DFT
by: Rong-Tyh Wang, et al.
Published: (1994)

A pipelined VLSI design of reed-solomon encoder and decoder
by: Chuan-Neng Cheng, et al.
Published: (1996)

VLSI architectures of pipelined viterbi decoder
by: LI, WEN-DA, et al.
Published: (1989)

Design and implementation of the VLSI circuit for LISCP-II
by: CAI, JIAN-CHUAN, et al.
Published: (1992)

Design of the Neuron Circuit for the Diffusion Network in VLSI
by: Chu, Ming-Ru, et al.
Published: (2005)

Circuit design of VLSI architectures for clustering analysis
by: Lai, Mao Fu, et al.
Published: (1995)

Electro-thermal simulation for design of VLSI circuits
by: 廖惇孟
Published: (2001)

Area-time-power view of VLSI pipelined wave digital filters
by: Israsena, Pasin
Published: (2001)

New algorithms for physical design of VLSI circuits
by: Lai, Minghorng
Published: (2011)

VLSI Circuit Design of Reed-Solomon Codec
by: Jhy-Yeu Chang, et al.
Published: (1994)

Systematic design solutions for analog VLSI circuits /
by: Huang, Shu-Chuan
Published: (1994)

CMOS VLSI circuits for imaging
by: Wang, Guoyu
Published: (1993)

Cannot write session to /tmp/vufind_sessions/sess_2r7b2ghe9kr1rrumt56kkj8a08