Design of Pipelined VLSI Circuits for Tolerating Timing Errors
碩士 === 國立東華大學 === 電子工程研究所 === 96 === Abstract Owing to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting more and more seve...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/85736205639217314454 |