Design of Pipelined VLSI Circuits for Tolerating Timing Errors

• Main Authors: Yi-Kai Wang, 王逸凱
• Other Authors: Chou-Chi Hsin
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/85736205639217314454

碩士 === 國立東華大學 === 電子工程研究所 === 96 === Abstract Owing to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting more and more severe. One of the challenges we are faced with is timing errors. As the clock rate is higher, the probability of timing errors gets higher too. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is more important when the system-on-chip era has become practical for many applications. This thesis proposes a new error resilient design for pipelined VLSI circuits to tolerate timing errors. In our design, a technique is presented to detect and correct the timing errors. Basically, we modify the pipeline buffer by adding appropriate control circuits to adjust to the timing error event. We have validated our idea by applying our technique to two example digital signal processing designs: an FIR filter and an IIR filter. We have simulated the two designs and implemented them with cell-based design flow. The results show that our designs add nearly no delay at a reasonable area cost.