| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 96 === The chip density and memory capacity are growing up with the nanotechnology. The area percentage of embedded memory in modern SOC design is highly increasing so the power consumption and test time of embedded memory becomes a critical problem. How to effectively speed up the embedded memory test and increase its yield are crucial issues for embedded memory testers. One of the traditional embedded memory test method is to meas-ure the supply current (Idd) in the quiescent state (IDDQ Test).This method fails in deep-submicron and even nano-scale device because the leakage current increases with the scaled-down of the gate oxide thickness. The other major test method is the March Test Algo-rithms, which are the mainly used approaches in embedded memory logic test. The disadvan-tage of this method is that the test time increases as the memory size grows. It will spend much more time on testing the embedded memory for chips with large memory size.
In this thesis, we utilize the multi-threshold CMOS (MTCMOS) technology to reduce the static leakage current in power-gating mode and accelerate the operation in active mode. A novel power gating method called Adaptive Data Retention CMOS (ADRCMOS) is proposed which can effectively reduce the power consumption from leakage current and has the func-tion of data retention. We apply the current test in sleep mode for CMOS logic with the pro-posed power gating architecture in the address decoder and SRAM, and propose a novel power gating address decoder and power gating SRAM.
We also propose a least significant bit (LSB) selective power gating address decoder archi-tecture, which can reduce the area overhead, reduce power consumption and increase the current testability. We can even reduce almost half of the time consumed in March Testing Algorithm. For the high resolution current test in sleep mode, we can reduce the testing time in several degrees and reduce more than 99% testing time.
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