Design for Fast and High-Resolution Current Testability of SRAM in Nanotechnology
碩士 === 國立彰化師範大學 === 電子工程學系 === 96 === The chip density and memory capacity are growing up with the nanotechnology. The area percentage of embedded memory in modern SOC design is highly increasing so the power consumption and test time of embedded memory becomes a critical problem. How to effectively...
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| Format: | Others |
| Language: | zh-TW |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98996416990683650469 |