Peak Current Reduction by Using Hybrid-Edge Clock Technique in the System Design Flow

• Main Authors: Tzi-Wei Kao, 高子為
• Other Authors: Tzung-Yi Wu
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/18478102636223471706

碩士 === 國立彰化師範大學 === 電子工程學系 === 96 === As process technology progresses to ultra deep sub-micron, the number of transistors in unit's area is promoted sharply. The number of transistors that simultaneous switching also increases in the circuit. In a SoC system, the designer minutely uses rising edge to acquire data; therefore too many Flip-Flops simultaneously renew the data and transmit the data to combination circuit. For this reason there are many issues that need to challenge in the ultra deep sub-micron circuit, such as the enormous peak current. The enormous peak current will cause the problems, such as electro migration, self-heat in chip, IR drop and ground bounce. If the switch time of circuits in each module can be staggered, then it can effective reduce the peak current. In this thesis, I propose a hybrid-edge clock technique that can decide some modules using rising triggered edge and some modules using falling triggered edge in order to reduce peak current. I proposed many algorithms（Integer Linear Programming, Greedy Algorithm 1, New Greedy Algorithm 1, Greedy Algorithm 2 and New Greedy Algorithm 2）to choose clock triggered edge in the circuit in each module. After the process of the algorithm, the peak current of the circuit can be effective reduced.