Peak Current Reduction by Using Hybrid-Edge Clock Technique in the System Design Flow
碩士 === 國立彰化師範大學 === 電子工程學系 === 96 === As process technology progresses to ultra deep sub-micron, the number of transistors in unit's area is promoted sharply. The number of transistors that simultaneous switching also increases in the circuit. In a SoC system, the designer minutely uses rising...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18478102636223471706 |