| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 96 === Multi-core architecture with built-in self-test (BIST) has become a design trend for VLSI chips due to their needs of high performance and high reliability. Efficient approaches for diagnosing fail cores and scan chains thus are imperative for yield enhancement. We propose in this thesis not only a new failing intellectual property and vector identification circuit (FIPVIC) for identifying failing cores and vectors of a scan-BIST multi-core chip but also an enhanced scan chain diagnosis scheme for scan-enable fault. The FIPVIC design uses the concepts of voter of the triple-module-redundancy (TMR) design and on-chip evaluation and comparison to find out which core and vector failed to the BIST test. The enhanced scan chain diagnosis scheme focuses on two diagnoses of scan-enable faults: the stuck-at-shift (SAS) fault and the stuck-at-capture (SAC) fault. In order to diagnose stuck-at shift fault, we propose two diagnosis methods that either use shifting-1-bit process to match the faulty behavior pattern or use direct comparison approach which compares the faulty response with the golden pattern. For diagnosing stuck-at capture fault, we propose a diagnosis method that uses fault dictionary-based diagnosis technique, convolution comparison score technique, statistics analysis, and simplified signal profiling technique. We create the dictionary by storing the scan output responses and use convolution comparison score technique to compare signatures of test response then calculate the score of each fault candidate cells. At last, statistics analysis and simplified signal profiling technique are used to supply for scoring the signature, which gets too low scores in convolution comparison. Experimental results show that the proposed FIPVIC for multi-core chip can efficiently (only took half time of the typical one) identify the failing core and vector with a small amount of area overhead. The proposed diagnosis approach for SAS can very precisely locate the faulty scan cell for most simulated benchmarks. Although the proposed approach for SAC cannot do as well as the approach for SAS, it still get quiet high success rate.
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