A Wide-Range Digital Synchronous Buffer with Programmable Duty Cycle
碩士 === 國立中央大學 === 電機工程研究所 === 96 === In view of the current SOC systems, a great deal of circuits is integrated on a chip and the clock signal is entirely distributed to synchronize the SOC systems. The clock synchronization circuits, hence, become an important issue. Clock skew will seriously influ...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95940703708990251204 |